This application claims the benefit of Korean Patent Application No. 2002-25625, filed May 9, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
1. Field of the Invention
The present invention relates to input/output buffers, and more particularly, to differential type input/output buffers and related methods.
2. Description of the Related Art
A semiconductor memory device typically includes various circuits. One such circuit is an input/output buffer. FIG. 1 is a block diagram of a conventional differential type input/output buffer. Referring to FIG. 1, the conventional differential type input/output buffer comprises a differential amplification portion 111 and an inverting portion 121.
A reference voltage Vref and an external signal IN are applied to the differential amplification portion 111. The external signal IN is converted into a complementary metal oxide semiconductor (CMOS) level voltage by the differential amplification portion 111, inverted by the inverting portion 121, and output as Vout.
The reference voltage Vref applied to the differential amplification portion 111 may vary as a result of external factors, for example noise. As a result, the common mode of the differential amplification portion 111 can vary. If the common mode of the differential amplification portion 111 varies, a relatively large amount of skew 221 and 231 may occur in the output signal Vout of the inverting portion 111 as shown in FIG. 2.
In other words, if the reference voltage Vref increases above a reference value, for example, 1.25 volts, the rising time of the output signal of the differential amplification portion 111 may become slow and the falling time of the output signal may become fast. Accordingly, the falling time of the output signal Vout of the inverting portion 121 may become slower (222) than the reference signal 211, and the rising time of the output signal may become faster (221) than the reference signal 211.
On the other hand, if the reference voltage Vref decreases below the reference value, the rising time of the output signal of the differential amplification portion 111 may become fast and the falling time of the output signal may become slow. Accordingly, the falling time of the output signal Vout of the inverting portion 121 may become faster (232) than that of the reference signal 211, and the rising time of the output signal may become slower (231) than that of the reference signal 211. Accordingly, a large amount of skew may occur in the output signal Vout of the inverting portion 121 as shown in FIG. 2.
As described above, a large amount of skew may occur in the output signal Vout of the inverting portion 121 as the reference voltage Vref applied to the amplifier 111 is changed. Semiconductor devices equipped with the input/output buffer can malfunction due to skew.
According to embodiments of the present invention, a buffer may have an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and outputs an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit, is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.
In this configuration, the power supply voltage and the ground voltage provided to the inverter can be adjusted responsive to the reference voltage so that if a reference voltage increases or decreases above or below the reference value, the resulting skew at the output signal of the input/output buffer may be decreased.
In other embodiments according to the invention, a method for reducing skew in a buffer includes receiving a power supply voltage, a ground voltage, and external signal and a reference voltage. An output signal is output responsive to the difference between the external signal and the reference voltage. The output signal is inverted responsive to the reference voltage.
According to certain embodiments of the invention, a differential type input/output buffer may have a differential amplification portion which receives an external signal and a reference voltage, amplifies the external signal and outputs the amplified signal. An inverting portion inverts the output of the differential amplification portion and outputs the inverted signal. A power source provides a power supply voltage to the inverting portion, and varies the quantity of electric charge provided to the inverting portion in response to the reference voltage. A ground voltage supply portion provides a ground voltage to the inverting portion, and varies the quantity of electric charge provided to the inverting portion in response to the reference voltage.
In other embodiments, a differential type input/output buffer may have a differential amplification portion which receives an external signal and a reference voltage, amplifies the external signal, and outputs the amplified signal. A pull-up portion receives the reference voltage and a power supply voltage, and outputs an output signal having the power supply voltage level in response to the reference voltage when the output signal of the differential amplification portion is logic low. A pull-down portion receives the reference voltage and a ground voltage, and outputs an output signal of the ground voltage level in response to the reference voltage when the output signal of the differential amplification portion is logic high.
In further embodiments, a differential type input/output buffer may have a differential amplification portion which receives an external signal and a reference voltage, amplifies the external signal, and outputs the amplified signal. An inverting portion inverts the output of the differential amplification portion and outputs the inverted signal. A power supply voltage supply portion receives the reference voltage, and delays the time for an output signal of the inverting portion to be transited from logic low to logic high if the reference voltage increases above a reference value when an output of the differential amplification portion is transited from logic high to logic low, and increases the time for an output signal of the inverting portion to be transited from logic low to logic high if the reference voltage decreases below the reference value.
In other embodiments, a differential type input/output buffer may have a differential amplification portion which receives an external signal and a reference voltage, amplifies the external signal, and outputs the amplified signal. An inverting portion inverts the output of the differential amplification portion and outputs the inverted signal. A power supply voltage supply portion receives the reference voltage, and increases the time for an output signal of the inverting portion to be transited from logic high to logic low if the reference voltage increases above a reference value when an output of the differential amplification portion is transited from logic low to logic high, and delays the time for an output signal of the inverting portion to be transited from logic high to logic low if the reference voltage decreases below the reference value.